1991-09-24
1993-02-23
James, Andrew J.
357 234, 357 238, H01L 2978, H01L 7152, H01L 4902
Patent
active
051894971
ABSTRACT:
This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.
REFERENCES:
patent: 3868187 (1975-02-01), Masuoka
patent: 4142926 (1979-03-01), Morgan
patent: 4258378 (1981-03-01), Wall
patent: 4290077 (1981-09-01), Ronen
patent: 4376947 (1983-03-01), Chin et al.
patent: 4573144 (1986-02-01), Countryman, Jr.
patent: 4630085 (1986-12-01), Koyama
patent: 4642881 (1987-02-01), Matsukawa et al.
patent: 4665418 (1987-05-01), Mizutani
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4872041 (1989-11-01), Sugiura et al.
patent: 5079603 (1992-01-01), Komori et al.
Hagiwara Takaaki
Komori Kazuhiro
Kume Hitoshi
Meguro Satoshi
Tsukada Toshihisa
Hitachi , Ltd.
James Andrew J.
Ngo Hgan Van
LandOfFree
Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2209489