Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1987-04-17

1989-01-10

Carroll, J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 45, 357 51, 357 59, 365154, H01L 2978, H01L 2702, H01L 2904

Patent

active

047977175

ABSTRACT:
Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

REFERENCES:
patent: 4209716 (1980-06-01), Raymond, Jr.
patent: 4453175 (1984-06-01), Ariizumi et al.
patent: 4524377 (1985-06-01), Eguchi
patent: 4535426 (1985-08-01), Ariizumi
patent: 4590508 (1986-05-01), Hirakawa et al.
patent: 4609835 (1986-09-01), Sakai et al.

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