Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1991-12-06

1992-12-15

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read only systems

Fusible

365208, 307443, 307542, 307564, 3072021, G11C 1700

Patent

active

051723379

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a semiconductor memory, and more particularly to a non-volatile semiconductor memory device of a fuse melting type.


BACKGROUND OF THE INVENTION

FIG. 1 shows a part of a fuse melting type non-volatile memory device proposed in Japanese Patent Application (Patent Application No. 63-204802) filed by the present inventor.
In FIG. 1, a memory cell 12 has a read-only N-channel MOS transistor (hereinafter called N-MOS) 3, an N-MOS 5 for melting a fuse, and a fuse 7 to be melted with current. Such memory cells 1 are formed on a chip and disposed in a matrix shape.
Each N-MOS 3 is formed as having, for example, a channel width 2 .mu.m, a channel length 2 .mu.m, a gate electrode film thickness 4000 .ANG., and a gate oxide film thickness 200 .ANG.. The gate terminal of the N-MOS 3 is connected to a read word line 9. The N-MOS 3 becomes conductive when data is read.
Each N-MOS 5 is formed as having, for example, a channel width 7 .mu.m, a channel length 1.0 .mu.m, a gate electrode film thickness 4000 .ANG., and a gate oxide film thickness 200 .ANG.. The gate terminal of the N-MOS 5 is connected to write word line 11. The N-MOS 5 becomes conductive when data is written.
As the characteristics of the N-MOS 5, the relation between a drain voltage V.sub.D and a drain current I.sub.D is shown in FIG. 2. Referring to FIG. 2, the N-MOS 5 causes a secondary breakdown at a drain voltage about 7 V while a power source voltage (about 5 V) is applied as a gate voltage V.sub.G. Namely, a snap back operation is performed. Under such a condition, the N-MOS 5 can flow a large current in the order of 80 mA. As seen from FIG. 2, the N-MOS 5 has a drain breakdown voltage of about 15 V when the gate terminal is set to the ground potential.
A serial connection of the N-MOS 3 and N-MOS 5 is serially connected between a read data line 13 and a ground wiring 15 connected to ground. The interconnection point C.sub.1 between these transistors 3 and 5 is connected to one end of the fuse 7 whose other end is connected to a write data line 17.
The fuse 7 is made of polysilicon having a thickness 4000 .ANG. same as that of the gate electrodes of the transistors 3 and 5. A narrow melting portion 7a at the center of the fuse 7 has a width 0.8 .mu.m and a length 2 .mu.m. The interconnection point C.sub.1 and a contact area C.sub.2 of the write data line (on the high voltage side of power source lines) 17 each are formed 2 .mu.m.times.2 .mu.m. Thus, the size of the memory cell 1 is about 140 .mu.m.sup.2 (20 .mu..times.7 .mu.) which is a considerably small occupying area.
The write data line 17 to which the other end of the fuse 7 is connected, is connected at its one end to a pad 19. Power is externally supplied via this pad 19 to melt the fuse 7. Namely, a voltage applied to the pad 19 (hereinafter called a melting voltage) is set such that only the N-MOS 5 connected to the fuse 7 to be melted takes the secondary breakdown state. Consider now the case where the fuse 7 (1) of a memory cell 1 (1) is to be melted. In this case, a word line 11 (1) is set to the power source voltage, and a word line 11 (2) is set to the ground potential. As a result, an N-MOS (1) turns on and an N-MOS (2) turns off. Under this condition, a melting voltage is applied to a pad 19 (I). This melting voltage is set to a value lower than the drain breakdown voltage of the N-MOS 5 (2), and higher than the secondary breakdown voltage of the N-MOS 5. Therefore, current flows only through the fuse 7 (1) and not through a fuse 7 (2), melting the fuse 7 (1) as will be described later more in detail.
An N-MOS 20 is connected between the write data line 17 and ground, the N-MOS 20 being turned on and off by a program signal PGM. This N-MOS 20 is made non-conductive by a low level program signal when data is written. On the other hand, when data is read, the N-MOS 20 is made conductive by a high level program signal to set the write data line to the ground potential.
The write data line 17 and the ground wiring (on the low volt

REFERENCES:
patent: 5065048 (1991-11-01), Asai et al.
patent: 5111075 (1992-05-01), Ferry et al.

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