Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-01-16

1998-02-10

Clawson, Jr., Joseph E.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518905, 36518907, G11C 1500

Patent

active

057176256

ABSTRACT:
In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

REFERENCES:
patent: 5220526 (1993-06-01), Giles et al.
patent: 5267190 (1993-11-01), Easley et al.
patent: 5321651 (1994-06-01), Monk
IEEE ISSCC Digest of Technical Papers, vol. 34, pp. 106-107, TAM 6.2, 1994, K. Kimura et al., "A Block Oriented RAM, Architecture".
IEEE ISSCC Digest of Technical Papers, vol. 36, pp. 46-47, WP 3.3, 1994; T. Hasegawa et al., "An Exp. DRAM with an and structured cell".

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