Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-07-28

2000-06-13

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

36523008, 36518905, G11C 800

Patent

active

060757493

ABSTRACT:
A semiconductor memory device comprises: an internal clock signal generating circuit that generates first and second internal clock signals for the internal timing control in response to an external clock; a first latch circuit that includes a first switching means to operate synchronously with the first internal clock signal and latches a plurality of command control signals for the internal operation control and outputs a plurality of latch command signals; a command decoding circuit that decodes the plurality of latch command signals and outputs a plurality of command decode signals; and a latch circuit that includes a second switching means to operate synchronously with the second internal clock signal, latches the plurality of command decode signals and outputs a plurality of predetermined mode signals. The internal clock signal generating circuit comprises a timing setting means for setting a timing between the first and second internal clock signals, and a clock width adjusting means for adjusting a pulse width of the first internal clock signal according to the timing of the second internal clock signal.

REFERENCES:
patent: 5808961 (1998-09-01), Sawada
patent: 5896341 (1999-04-01), Takahashi
patent: 5898331 (1999-04-01), Fujita

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