Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-11-05

2000-08-15

Mai, Son

Static information storage and retrieval

Format or disposition of elements

365 63, 365226, G11C 502

Patent

active

061046272

ABSTRACT:
The present invention relates to a semiconductor memory device having a memory cell array of a split-operation mode.
The semiconductor memory device comprises a semiconductor chip having first through fourth sides, a first interconnection disposed along the first side of the semiconductor chip and supplied with a source potential level or a ground potential level, a second interconnection disposed along the second side opposed to the first side and supplied with the source potential level or the ground potential level, and a plurality of sub-array regions disposed between the first interconnection and the second interconnection. A plurality of memory cells and a plurality of sense amplifiers respectively connected to the memory cells are disposed in each of the sub-array regions. The memory cells and the sense amplifiers disposed in one of the sub-array regions are activated in response to the potential level supplied to the first interconnection. The memory cells and the sense amplifiers disposed in another one of the sub-array regions are activated substantially simultaneously with the memory cells and the sense amplifiers disposed in the above one of the sub-array regions in response to the potential level supplied to the second interconnection.

REFERENCES:
patent: 5231607 (1993-07-01), Yoshida
patent: 5293334 (1994-03-01), Shimizu
patent: 5293559 (1994-03-01), Kim et al.
patent: 5321646 (1994-06-01), Tomishima
patent: 5321658 (1994-06-01), Ishimura et al.
patent: 5422853 (1995-06-01), Miyamoto
patent: 5535152 (1996-07-01), Han
patent: 5604710 (1997-02-01), Tomishima

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