Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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36518526, G11C 1604

Patent

active

061282235

ABSTRACT:
A semiconductor memory device includes a memory cell and first and second electrodes. The memory cell has a floating gate formed on a semiconductor substrate via a gate insulating film to be insulated from a remaining part, and a control gate formed on the floating gate via an isolation insulating film. The first electrode is formed on the floating gate via a first insulating film in a region of the floating gate except for a channel region for constituting the memory cell. The second electrode is formed on the floating gate via a second insulating film in a region of the floating gate except for the channel region for constituting the memory cell. When a predetermined voltage is applied to the first and second electrodes, a tunnel current flows through the first and second insulating films.

REFERENCES:
patent: 4661833 (1987-04-01), Mizutani
patent: 5338952 (1994-08-01), Yamauchi
patent: 5414286 (1995-05-01), Yamauchi
patent: 5596529 (1997-01-01), Noda et al.

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