Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1986-12-03

1987-12-01

Edlow, Martin H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 42, 365190, 365 51, H01L 2978

Patent

active

047107898

ABSTRACT:
In a semiconductor memory device, memory cells of a first column each comprising an N-channel FET are connected to a first bit line, and memory cells of a second column each comprising a P-channel FET are connected to a second bit line. The first bit line and the second bit line are connected to complementary terminals of a sense amplifier to form a folded-bit line pair. A work line is connected to the gate of the N-channel FET of one of the memory cells of the first column and to the gate of the P-channel FET of one of the memory cells of the second column. The word line is selectively provided with a first voltage to make conductive the N-channel FET connected thereto and to make nonconductive the P-channel FET connected thereto, or a second voltage to make conductive the P-channel FET connected thereto and to make nonconductive the N-channel FET connected thereto, or a third voltage to make nonconducitve both the N-channel FET and the P-channel FET connected thereto.

REFERENCES:
patent: 4545037 (1985-10-01), Nakano et al.
patent: 4604639 (1986-08-01), Kinoshita
patent: 4641166 (1987-02-01), Takemae et al.
Kunio Nakamura et al., "Buried Isolation Capacitor (BIC) Cell for Megabit MOS Dynamic RAM", IDEM 84, pp. 236-239.

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