Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

Patent

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Details

36523001, 36523002, 36523006, 36523008, G11C 800

Patent

active

060698357

ABSTRACT:
A semiconductor memory device comprises a first core section including a plurality of memory cell arrays, a second core section including a plurality of memory cell arrays and provided below the first core section, a third core section including a plurality of memory cell arrays and provided in a right side of the first core section, and a fourth core section including a plurality of memory cell arrays and provided in a right side of the second core section, wherein at least a part of the memory cell arrays of the first core section and at least a part of the memory cell arrays of the fourth core section are simultaneously activated, and at least a part of the memory cell arrays of the second core section and at least a part of the memory cell arrays of the third core section are simultaneously activated.

REFERENCES:
patent: 5625599 (1997-04-01), Okamura
patent: 5732040 (1998-03-01), Yabe
patent: 5740120 (1998-04-01), Okamura
patent: 5748201 (1998-05-01), Nagasaka
patent: 5838603 (1998-11-01), Mori et al.
patent: 5862096 (1999-01-01), Yasuda et al.
patent: 5890197 (1999-03-01), Nagasaka

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