Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518525, 36518518, G11C 1606

Patent

active

060698241

ABSTRACT:
A plurality of pull-down transistors, each grounding a source line at discrete positions, are provided in order that current, flowing from bit lines through some of nonvolatile memory cells having lower threshold voltages into the source line, is not concentrated at a single pull-down transistor in a source line driver during a read cycle.

REFERENCES:
patent: 5406521 (1995-04-01), Hara
patent: 5661686 (1997-08-01), Gotou
patent: 5912845 (1999-07-01), Chen et al.
patent: 5936891 (1999-08-01), Sekiguchi

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