Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

365222, 365233, 365239, G11C 800

Patent

active

055351697

ABSTRACT:
A semiconductor memory device includes a plurality of banks each having a memory cell array and sense amplifiers, a data input/output circuit and an address circuit. A first part of the device receives control signals from an outside of the semiconductor memory device and generates a refresh signal therefrom. A second part generates bank select signals in response to the refresh signal, the bank select signals being used to select the plurality of banks. A third part receives the bank select signals and generating latch enable signals therefrom, the latch enable signals driving the sense amplifiers provided in the plurality of banks. A refresh operation is carried out by activating the sense amplifiers by using the latch enable signals.

REFERENCES:
patent: 5216635 (1993-06-01), Kass et al.
patent: 5251176 (1993-10-01), Komatsu
patent: 5251178 (1993-10-01), Childers
patent: 5335201 (1994-08-01), Walther et al.

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