Semiconductor memory device

Static information storage and retrieval – Magnetic bubbles – Guide structure

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365185, H01L 2978, G11C 1134

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046654186

ABSTRACT:
A semiconductor memory device includes n.sup.+ -type first and second semiconductor regions which are separately formed in the surface area of a p-type semiconductor substrate, a floating gate and a control gate. The second semiconductor region acting as a drain in a data readout mode is composed of a main portion, and an additional portion having an impurity concentration lower than that of the main portion and formed in contact with the main portion and a channel region.

REFERENCES:
patent: 4070687 (1978-01-01), Ho
patent: 4258378 (1981-03-01), Wall
IBM Technical Disclosure Bulletin, vol. 16, #2, p. 690, by James, Jul. 1973.
Patent Abstracts of Japan, 17.11.1981, vol. 5, No. 179, Abstract 56-104473.
Wada, "Charge Storage Characteristics of MIS-FETs with Floating Gate," Electronics and Communications in Japan, vol. 59-C, No. 8, pp. 101-109, 1976.
Gaind, "High-Performance FET Device Structure and Method," IBM Technical Disclosure Bulletin, vol. 15, No. 4, pp. 1342-1342a, Sep. 1971.

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