Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1990-11-15

1993-07-20

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518901, 36518905, G11C 700, G11C 800

Patent

active

052299716

ABSTRACT:
A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, registers and a control unit. The control unit allows the write operational mode of the column decoder to switch. In the ordinary write operational mode, data in the n registers are written into the active memory cells of the n memory cell columns in on column block selected by the column decoder, respectively. In the block write mode, data in the n registers are written into active memory cells of the n memory cell columns in the 2.sup.N column blocks selected by the column decoder, respectively. Another semiconductor memory device comprises N memory units. Each memory unit comprises a memory cell array, a row decoder, a first column decoder, a second column decoder, a data input terminal, registers and a control circuit. The control circuit is operative to allow the operational mode. When the device is in the ordinary mode, data latched in the register is written into one memory cell connected to one word line selected by the row decoder of one column selected by the first column decoder of column blocks selected by the second decoder. While when the device is in the block write mode, data latched in the register is written at the same time into j memory cells connected to one word line selected by the row decoder of column blocks selected by the second column decoder.

REFERENCES:
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patent: 4926385 (1990-05-01), Fujishima et al.
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Jeff Mailloux et al., "Speed Memory, Ease Timing Requirements with VRAM Functions", p. 96, middle column, line 29-p. 98, left column, line 34; FIGS. 1,2; table 1, Electronic Design, vol. 37, No. 24, Nov. 23, 1989, Hasbrouck Heights, N.J., pp. 95-99.
Donald T. Wong et al., "An 11-ns 8K.times.18 CMOS Static RAM with 0.5-.mu.m Devices", FIG. 8, IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, N.Y., pp. 1095-1103.

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