Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-08-09

1998-06-16

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

365202, 365207, G11C 800

Patent

active

057682143

ABSTRACT:
A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.

REFERENCES:
patent: 4727516 (1988-02-01), Yoshida et al.
patent: 5414672 (1995-05-01), Ozeki et al.
patent: 5544115 (1996-08-01), Ikeda

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