Semiconductor memory device

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...

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Details

36523003, 36523006, 365203, 365222, G11C 800, G11C 700

Patent

active

054954541

ABSTRACT:
A memory device comprises a plurality of memory cell array blocks (CAB1) each having at least one word line (WL11) and associated with a word line drive circuit (PD1a, WD1a, RD1), a block select circuit (BSa) for selectively outputting a block select signal (SL1s) corresponding to one of the memory cell array blocks, an address buffer (AB1a) for outputting word address signals (AddR1) to the memory cell array blocks wherein the word line drive circuit is associated with an address latch circuit (AL1a) which latches and continuously outputs one of the word address signals thereto, the block select signal activates the address latch circuit for latching one of the word address signals, the word line drive circuit continuously activates the word line according to an output signal (AL1aout) of the address latch circuit and deactivates the word line only when the block select signal (SL1s) corresponding to the memory cell array block is output from the block select circuit.

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Hiroaki Nambu, et al., 4-K Bit Bipolar Ram with On-Chip Address Latch Function, Electronics and Communications in Japan, Oct. 1987, vol. 70, No. 10, pp. 45-54.

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