Semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36523006, 36523008, 36518901, 36518905, 36518907, G11C 700

Patent

active

061446165

ABSTRACT:
A semiconductor memory device operating in synchronism with a clock includes an address latch&comparator part latching a first address signal associated with a write command and comparing the first address signal with a second address signal associated with a read command. A write data buffer part holds a data signal associated with the write command. The data signal held in the write data buffer part is read as a data signal requested by the read command when the first and second address signals coincide with each other.

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patent: 5917760 (1999-06-01), Millar
patent: 5917772 (1999-06-01), Pawlowski
patent: 5966343 (1999-10-01), Thurston
"Revolutionary SRAM Architecture and New ZBT (Zero Bus Turnaround) Product Family".
"128K.times.36 Bit Pipelined BurstRAM Synchronous Fast Static RAM",Motorola Semiconductor Technical Data, pp. 1-2.

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