Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1980-09-30

1984-05-08

Popek, Joseph A.

Static information storage and retrieval

Powering

365230, G11C 1140

Patent

active

044478950

ABSTRACT:
A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of the row decoders for controlling the conduction state of the switching MOS transistors.

REFERENCES:
patent: 3803554 (1974-04-01), Bock et al.
patent: 3909808 (1975-09-01), Cochran et al.
patent: 4074237 (1978-02-01), Spampinato
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4151611 (1979-04-01), Swgawara et al.
patent: 4194130 (1980-03-01), Moench
Posa, "What to Expect Next: A Special Report", Electronics, May 22, 1980, pp. 119-129.
Dockerty et al., "Enhancement/Depletion Decoder Circuit", IBM Tech. Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, pp. 1681-1682.
Huffman et al., "Memory Address Decode Circuit", IBM Technical Disclosure Bulletin, vol. 19, No. 1, Jun. 1976, pp. 28 and 29.

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