Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1993-06-09

1994-02-22

Clawson, Jr., Joseph E.

Static information storage and retrieval

Interconnection arrangements

365 52, 365 72, 257 69, 257393, 257758, 257773, G11C 506

Patent

active

052894045

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells arranged along a word line. Each memory cell is constituted by a flip-flop formed by a pair of driver transistors of a first conductivity channel and a pair of load transistors of a second conductivity channel. The load transistors have an active layer formed by a semiconductor thin film.
A power line connected to the load transistors includes a first metal layer that extends in a direction parallel to the word line and connections, arranged at intervals along the word line, between the first metal layer and the semiconductor thin film.
A ground line is connected to the driver transistors and includes a second metal layer that extends in a direction parallel to the word line and a connecting portion that is connected to the second metal layer and extends in a direction perpendicular to the word line.
This arrangement prevents the ON current of the load transistors from being reduced thereby increasing the ON/OFF current ratio without increasing the area required for the memory device. Accordingly, data retention characteristics can be improved without decreasing the degree of circuit integration.

REFERENCES:
patent: 4034243 (1977-07-01), Love et al.

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