Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

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36523006, G11C 700

Patent

active

054105129

ABSTRACT:
A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.

REFERENCES:
patent: 4701885 (1987-10-01), McElroy
patent: 5121354 (1992-06-01), Mandalia
patent: 5241510 (1993-08-01), Kobayashi
patent: 5251180 (1993-10-01), Ohshima
patent: 5257235 (1993-10-01), Miyamoto
N. Kushiyama et al, "500 Mbyte/sec Data-Rate 512 Kbits.times.9 DRAM Using a Novel I/O Interface," 1992 Symposium on VLSI Circuits Digest of Technical Papers 7-4, pp. 66-67, dated Jun. 4, 1992.

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