1982-06-01
1985-09-10
Fears, Terrell W.
Excavating
365201, G11C 1300
Patent
active
045410909
ABSTRACT:
A large capacity memory is improved so as to reduce its testing time length. Memory arrays are divided into a plural number of memory blocks having common address signal lines and common input/output lines, each memory block is provided with respective comparators thereby enabling testings of the plural number of memory blocks parallelly at the same time.
REFERENCES:
patent: 4317200 (1982-02-01), Wakatsuki et al.
Fears Terrell W.
Matsushita Electric - Industrial Co., Ltd.
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