Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1989-05-08

1990-12-18

Hille, Rolf

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 42, 357 51, 357 236, 357 2311, 365149, H01L 2702, H01L 2906, H01L 2968, G11C 1124

Patent

active

049790137

ABSTRACT:
A semiconductor memory device having a memory cell array of a folded bit line configuration comprises memory cells, two each of which are formed to share a contact hole and surrounded by an isolation trench, and data charge storage capacitance formed on the entire sidewall of the isolation trench except a part of the isolation trench where an isolation oxide film is formed on the sidewall of the isolation trench. The isolation oxide film separates the two memory cells from each other. One word line passes through a region for one bit memory cell, and two bit lines pass through a region for one bit memory cell.

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H. Shichijo et al. "Polysilicon Transistors in VLSI MOS Memories", IEDM 84, pp. 228-231.
IBM Technical Disclosure Bulletin, vol. 27, #12, May 1985, pp. 7051-7052.
Horiguchi et al., "A One Mb DRAM with a Folded Capacitor Cell Structure", IEEE International Solid State Circuits Conference Digest of Technical Papers, Coral Gables, pp. 244-245, 335, Feb. 1985.
Sunami, "Cell Sructures for Future DRAM's", International Electron Devices Meeting, Washington, D.C., pp. 694-697, Dec. 1-4, 1985.
32nd ISSCC Sec. XVII, 1985 IEEE International Solid State Circuits Conf. Digest of Technical Papers, Coral Gables, FL., FEb. 1985, pp. 244-255; Aoriguchi et al.

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