Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-12-27

1997-05-13

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, G11C 700

Patent

active

056299028

ABSTRACT:
In an asynchronous type memory device for controlling a plurality of bytes independently, even if the byte control signal changes in the write cycle, the automatic power-down can be released and further the data can be read after data have been written. When data are transferred from the input/output terminals I/OUBm and I/OLBn to the internal data buses DbusUB and DbusLB through the upper byte data input buffers DinUBm and the lower byte input buffers DinLBn, the change detecting sections UWTD and LWTD generate the write start synchronous pulse .phi.BWS and the write end synchronous pulse .phi.BWE on the basis of the logical result of the write request signal /WE and the control signal /UB or /LB. Therefore, when the data are written and read for each byte independently, data can be written in and read from the memory cells irrespective of the data conditions. Further, the written data can be read immediately without changing the addresses.

REFERENCES:
patent: 5289408 (1994-02-01), Mimura
patent: 5402390 (1995-03-01), Ho
patent: 5414672 (1995-05-01), Ozeki
patent: 5477491 (1995-12-01), Shirai

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1390946