Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-03-18

1999-06-29

Mai, Son

Static information storage and retrieval

Interconnection arrangements

365149, 365205, 365206, G11C 506

Patent

active

059177454

ABSTRACT:
A semiconductor memory device according to this invention has a hierarchical bit line structure where a plurality of local bit lines are provided in parallel to each global bit line and some of the local bit lines in the column direction are connected to the global bit line. Such memory device further has an open bit line structure where global bit lines are provided on both sides of sense amplifiers, and has bit-line transfer circuits, provided between the global bit lines and the sense amplifiers, for isolating the global bit lines from the sense amplifiers when the sense amplifiers are activated. The use of the hierarchical bit line structure in combination with the open bit line structure enhances the layout efficiency of memory cells, and the provision of the bit-line transfer circuits overcomes a problem of erroneous data reading which would otherwise be caused by bit line noise inherent to the open bit line structure.

REFERENCES:
patent: 5495440 (1996-02-01), Asakura
patent: 5561626 (1996-10-01), Fujii
patent: 5682343 (1997-10-01), Tomishima et al.
patent: 5715189 (1998-02-01), Asakura
patent: 5757692 (1998-05-01), Suh

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