Semiconductor memory device

Static information storage and retrieval – Magnetic bubbles – Guide structure

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357 71, 365182, H01L 2702

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active

048090468

ABSTRACT:
A static-type semiconductor memory device having a three-layer structure: gate-electrode wiring lines being formed from a first conductive layer of, for example, polycrystalline silicon; word lines, ground lines, and power supply lines being formed from a second conductive layer of, for example, aluminum; and bit lines being formed from a third conductive layer of, for example, aluminum. The bit lines extending in a column direction, and the ground lines extending in a row direction. Thus, providing an improved degree of integration, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles.

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patent: 4376983 (1983-03-01), Tsaur et al.
patent: 4453175 (1984-06-01), Ariizumi et al.
patent: 4458406 (1984-07-01), DeLamoneda et al.
IEEE International Conference on Circuits and Computers, vol. 1 of 2, Oct. 1-3, 1980, pp. 4-11, "Future Directions in MOSFET Random Access Memories" European Search Report, The Hague, 9/19/85 Examiner: M. L. Odgers.
IEEE Journal of Solid-State Circuits, vol. SC-15, No. 5, Oct. 1980, pp. 854-861, Ohzone et al., "An 8K.times.8 Bit Static MOS RAM Fabricated by n-Mo S
-well CMOS Technology".

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