Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1995-03-22

1995-12-12

Beausoliel, Jr., Robert W.

Excavating

G06F 1100

Patent

active

054756928

ABSTRACT:
Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

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patent: 5016220 (1991-05-01), Yamagata
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patent: 5117393 (1992-05-01), Miyazawa et al.
patent: 5185744 (1993-02-01), Arimoto et al.
patent: 5208778 (1993-05-01), Kumanoya et al.
patent: 5231605 (1993-07-01), Lee

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