Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-08-12

1999-11-23

Zarabian, Amir

Static information storage and retrieval

Addressing

Sync/clocking

365236, G11C 800

Patent

active

059912316

ABSTRACT:
An internal synchronous signal generating circuit outputs the internal synchronous signals ICLK1, ICLK2. A burst counter outputs an internal column address signal IADD and the lowermost internal column address signal IY0. A first and second D-F/Fs input an output of the input buffer and drives a first write bus (WBUS) in synchronization with the ICLK1. An inverting element inputs IY0. Inverting elements input outputs of the first and second D-F/Fs and drives a second write bus (WBUS). A transistor TG1 is connected between the first WBUS and second D-F/F. The gate is connected to the output of the first inverting element. A transistor TG2 is connected between the output of the second inverting element and second D-F/F with IY0 connected to the gate. A column decoder inputs IADD and outputs a column switch YSW. Sense amplifiers input the YSW and the second WBUS. A memory cell array is connected to the sense amplifiers through a bit line. By this device, the maximum consumptive current amount or an average consumptive current in the burst can be reduced.

REFERENCES:
patent: 5621698 (1997-04-01), Lee
patent: 5886553 (1999-03-01), Matsui

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