Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1986-08-12

1988-10-18

Popek, Joseph A.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

047792272

ABSTRACT:
A semiconductor memory device having data buses for connecting memory cells in memory cell arrays with input/output buffer circuit includes a plurality of memory cell arrays having repetitive patterns. In the device, a plurality of column decoders are adjacent to the memory cell arrays and have repetitive patterns. A portion of the column decoders is displaced from a regular location in the column decoder to a separate location on a substrate of the semiconductor memory device to leave a blank portion in the column decoder. The device also includes an input/output buffer circuit, data buses for connecting the memory cell arrays to the corresponding input/output buffer circuit through spaces outside the column decoders including the blank portion, and conductors for connecting the displaced portion of column decoders located in the separate location to the corresponding memory cell arrays through spaces outside the column decoders including the blank portion.

REFERENCES:
patent: 3936812 (1976-02-01), Cox et al.

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