Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1995-09-19

1996-12-24

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 326108, G11C 800

Patent

active

055879594

ABSTRACT:
It is an object to provide reduction of power consumption and/or speed-up of a semiconductor memory device. Different subdecode signals are supplied to respective blocks BL.sub.1 -BL.sub.m forming a memory cell array. The subdecode signals are generated in subdecode signal generating circuits SDB1.sub.1 -SDB1.sub.m provided corresponding to the respective blocks BL.sub.1 -BL.sub.m from addresses BS.sub.1 -BS.sub.m for block selection and addresses SDA.sub.1, SDA.sub.2 for subdecode signal provided respectively to the blocks. The subdecode signals are supplied only to subdecode circuits of one block specified by the address for block selection, and the number of subdecode circuits allotted to one subdecode signal generating circuit and the length of signal lines can be reduced.

REFERENCES:
patent: 4542486 (1985-09-01), Anami et al.
patent: 4958326 (1990-09-01), Sakurai
patent: 5406526 (1995-04-01), Sugibayashi
patent: 5416748 (1995-05-01), Fujita
NEC Technical Journal, vol. 47, No. 3, pp. 69-73, 1994, Y. MATSUI, et al., "Development of 64 M BIT DRAM".

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