1987-12-02
1991-02-19
Wojciechowicz, Edward J.
357 235, 357 236, 357 41, 357 55, 357 90, H01L 2710
Patent
active
049948890
ABSTRACT:
A semiconductor memory device includes a memory cell array comprised of a plurality of memory cells each having a single transfer transistor and a single capacitor and a peripheral circuit including a plurality of drive transistors and adapted to drive the memory cell. The source and drain regions of the transfer transistor have an impurity concentration lower in level than that of the source and drain regions of the drive transistor.
REFERENCES:
patent: 4364075 (1982-12-01), Bohr
patent: 4413401 (1983-11-01), Klein et al.
patent: 4536944 (1985-08-01), Bracco et al.
Fujitsu-Patent Abstracts of Japan, vol. 6, No. 52 (E-100) [930] 4/7/82; JP-A-56 164570 17-12-1981.
Pp. 463 and 467 from the IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983.
Taniguchi et al., "Fully Boosted 64K Dynamic RAM With Automatic and Self-Refresh," IEEE Journal of Solid-States Circuit, vol. SC-16, No. 5, pp. 492-498, Oct. 1981.
Smayling et al., "256-K Dynamic RAM is More Than Just an Upgrade," Electronics, vol. 56, No. 17, pp. 135-137, Aug. 25, 1983.
Shinozaki Satoshi
Takeuchi Yukio
Kabushiki Kaisha Toshiba
Wojciechowicz Edward J.
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