Static information storage and retrieval – Addressing
Patent
1983-05-11
1985-04-02
Popek, Joseph
Static information storage and retrieval
Addressing
365226, G11C 1140
Patent
active
045091480
ABSTRACT:
A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of said row decoders for controlling the conduction state of the switching MOS transistors.
REFERENCES:
patent: 3803554 (1974-04-01), Bock et al.
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4151611 (1979-04-01), Sugawara et al.
patent: 4194130 (1980-03-01), Moench
Asano Masamichi
Iwahashi Hiroshi
Popek Joseph
Tokyo Shibaura Denki Kabushiki Kaisha
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