Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1984-12-13

1987-02-24

Edlow, Martin H.

357 41, 357 51, 357 55, 357 231, H01L 2978, H01L 2702

Patent

active

046461183

ABSTRACT:
A semiconductor memory device, such as a MOS dynamic RAM device, having memory cells each comprising a transfer gate transistor and a capacitor. The capacitor is a so-called groove-type capacitor and has a conductive layer formed on an insulation film attached to the inside surface of a groove formed on a semiconductor substrate. The conductive layer is electrically coupled to the source of the transfer gate transistor. The capacitance of the capacitor is formed between the conductive layer and a second conductive layer formed on the conductive layer via an insulation film, and/or between the conductive layer and the semiconductor substrate.

REFERENCES:
patent: 4466180 (1984-09-01), Soclof
patent: 4507159 (1985-03-01), Erb
Patents Abstracts of Japan, vol. 7, No. 72 (E-166) (1217), Mar. 25th, 1983; & JP-A-583260 (Fujitsu K.K.) Jan. 10, 1983, Abstract; figs. 4, 5.
Patents Abstracts of Japan, vol. 5, No. 99 (E-63) (771), Jun. 21, 1981; & JP-A-5643753 (Nippon Denshin Denwa Kosha) Apr. 22, 1981, Abstract; figs. 2a, 4a, 4b.
B. J. Masters: "Reduction of Alpha-Induced Soft Errors In Dynamic Memories" IBM Technical Disclosure Bulletin, vol. 22, No. 8a, Jan. 1980, pp. 3208-3209, Armonk, N.Y., US; p. 3208, paras. 2, 3; figs.

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