Semiconductor memory device

Static information storage and retrieval – Addressing – Byte or page addressing

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Details

365207, G11C 800, G11C 702

Patent

active

060612975

ABSTRACT:
A semiconductor memory device is provided which is capable of reducing the peak current of sense-amplifiers in the normal access mode operation and capable of a high speed access. The system comprises two types of sense-amplifiers 200 and 201 and a sense-amplifier control circuit for controlling activation start and finish time. Depending upon the access mode, the activation start time and the activation finish time for these sense-amplifiers and are shifted by a sense-amplifier control circuit, which can modify a one-shot-pulse signal generated by an ATD into an optional pulse width and a route for transmitting are altered for data obtained in the normal access mode operation and data obtained in the page access mode operation are transmitted by selected routes by a page-decoder, a sense-amplifier selection circuit, and a latch selector.

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