Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1993-09-10

1995-06-06

Popek, Joseph A.

Static information storage and retrieval

Format or disposition of elements

365 63, 365154, 257773, 257775, G11C 2900

Patent

active

054228395

ABSTRACT:
A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically. In this case, the offset voltage of the sense amplifiers decreases significantly.

REFERENCES:
patent: 4881203 (1989-11-01), Watanabe et al.
patent: 4958325 (1990-09-01), Nakagome et al.
patent: 5061980 (1991-10-01), Uchida
patent: 5140550 (1992-08-01), Miyaska et al.
patent: 5151761 (1992-09-01), Takebuchi
patent: 5175604 (1992-12-01), Nogami
patent: 5228000 (1993-07-01), Yamagata
patent: 5295114 (1994-03-01), Kobayashi
Hirose et al., "A 20ns 4Mb CMOS SRAM with Hierarchical Word Decoding Architecture", 1990 IEEE ISSCC pp. 132-133 Feb. 15, 1990.

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