1983-12-23
1986-08-05
James, Andrew J.
357 84, 357 29, 357 51, 357 41, 357 59, H01L 2993
Patent
active
046046399
ABSTRACT:
A semiconductor memory device comprising a semiconductor substrate of one conductivity type, memory cells each including a semiconductor impurity region of a conductivity type opposite to that of the substrate formed in the semiconductor substrate, a charge storage portion formed in the semiconductor substrate, and a gate portion to form a channel in the semiconductor substrate between the semiconductor impurity region and the charge storage portion, and a metal conductive layer. In order to reduce soft errors of the memory device caused by alpha particles from package materials, the metal conductive layer overlaying the charge storage portion is formed so as to have a width greater than the minimum width used in an integrated circuit at a portion thereof overlaying the substantial part of the charge storage portion.
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James Andrew J.
Small, Jr. Charles S.
Tokyo Shibaura Denki Kabushiki Kaisha
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