Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-12-09

2000-02-01

Nelms, David

Static information storage and retrieval

Format or disposition of elements

365 63, 36523003, G11C 502

Patent

active

060210613

ABSTRACT:
At least one of the row- and column-selection mechanisms, including row- and column decoders, respectively, of a DRAM has a core circuit array and a control circuit array adjacent to each other. The core circuit array has an m-number of core circuit units which are substantially equivalent to each other, and each of which consists of an n-number of core circuits forming the decoders, respectively. The control circuit array has an m-number of control circuit units which are substantially equivalent to each other, and are connected to the core circuit units by interconnection wiring lines, respectively. The core circuit units and the control circuit units are arranged in a first direction with first and second pitches, respectively, which differ from each other. The second pitch is smaller than the first pitch, so that an additional region derived from the difference between the pitches is arranged along with the control circuit units in the first direction, and lead-out wiring lines from the core circuit array are arranged in the additional region.

REFERENCES:
patent: 5280441 (1994-01-01), Wada et al.
patent: 5517442 (1996-05-01), Kirihata et al.
patent: 5636158 (1997-06-01), Kato et al.
Watanabe, et al. "A 286 mm.sup.2 256 Mb DRAM with x32 Both-Ends DQ," IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996; pp 567-574.

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