Semiconductor memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36518911, G11C 1134

Patent

active

049842153

ABSTRACT:
In a semiconductor memory device comprising a memory cell matrix having memory cells connected to word lines and bit lines and arranged in rows and columns, an initialize circuit is responsive to an initialize signal to set all the bit lines to predefined one of High level and Low level, and to raise the word line selected by the output of a row address decoder and then to raise other word lines sequentially. As a result, the memory cells are initialized sequentially word line by word line.

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