Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-07-28

1999-07-27

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

365203, G11C 700

Patent

active

059301970

ABSTRACT:
A semiconductor memory device is provided which is able to supply data at high speed to a microprocessor (MPU) without being affected by the dispersion of power supply voltage, temperature and production process conditions. A semiconductor chip includes an address buffer, a decoder, a word driver, data lines, a sense amplifier, a main amplifier, an output buffer, and a PLL to which an external clock is applied. The PLL generates controls signals .PHI..sub.1 through .PHI..sub.7 with their phases shifted in turn, and supplies them to those internal circuits ranging from the address buffer to the output buffer. The PLL can control the phases of these control signals to be constant without being affected by the variations of temperature and power supply voltage. Thus, the internal circuits are precharged or equalized by the control signals, and then operated by the control signals to amplify data signal in turn. Therefore, the operating cycle time can be shortened as compared with the access time, and the access time can be kept constant.

REFERENCES:
patent: 4807190 (1989-02-01), Ishii
patent: 5400282 (1995-03-01), Suzuki
patent: 5412615 (1995-05-01), Noro
Halkias et al, "Integrated Electronics: Analog and Digital Circuits and Systems", 1972, p. 488.
Y. Unekawa et al, "A 110MHz/1MBIT Synchronous Tag Ram", Symposium On VLSI Circuits, 1993, pp. 15-16.
K. Nakamura et al, "A 220MHz Pipelined 16Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator", IEEE International Solid-State Circuits Conference--Digest Of Technical Papers, 1994, pp. 258-259.
J.G. Maneatis et al, "Precise Delay Generation Using Coupled Oscillators", IEEE International Soild-State Circuits Conferece--Digest of Technical Papers, 1993, pp. 118-119.

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