1988-11-15
1989-07-04
James, Andrew J.
357 231, 357 234, 357 2311, 357 41, 357 51, 357 55, 357 59, H01L 2978, H01L 2702, H01L 2704
Patent
active
048455393
ABSTRACT:
A highly integrated semiconductor memory device having one transistor type memory cells is disclosed. The capacitor and transistor of the memory cell is provided within and around one trench formed in the semiconductor substrate. The channel region of the transistor is positioned along the side wall of the trench with a ring shape in the plan view and the capacitor element is surrounded by the transistor within the trench.
REFERENCES:
patent: 4630237 (1986-12-01), Miura et al.
patent: 4651184 (1987-03-01), Malhi
patent: 4672410 (1987-06-01), Miura et al.
Chang et al., "Vertical FET Random-Access Memories With Deep Trench Isolation", IBM Technical Disclosure Bulletin, vol. 22, No. 8B, Jan. 1980.
IEEE Report, San Francisco Meeting-Dec. 1982, IEDM 82, pp. 786-787 and 806-808.
James Andrew J.
NEC Corporation
Ngo Ngan Van
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