Semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking

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36518912, 365240, G11C 804

Patent

active

053813782

ABSTRACT:
A semiconductor memory circuit includes a memory cell array for storing data, and a bit structure selection circuit for performing a data transfer between the memory cell array and an external device by constructing the data in units of one bit or in units of two bits. The bit structure selection circuit includes a selector for selectively modifying a phase of a first clock signal and a second clock signal in response to a mode signal, and shift register for modifying a shift width of a memory selection signal in response to the first clock signal and the second clock signal supplied through the selector.

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patent: 4987559 (1991-01-01), Miyauchi et al.
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patent: 5260905 (1993-11-01), Mori
patent: 5265063 (1993-11-01), Kogure
patent: 5285409 (1994-02-01), Hwangbo et al.
IBM Technical Disclosure Bulletin; Memory Architecture with Flexibility In Bit-Wide Outputs, vol. 31, No. 12, May 1989, pp. 174-175.

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