Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1987-05-21

1988-09-13

James, Andrew J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 59, 357 42, 357 237, 365182, 365186, H01L 2978, H01L 2904, H01L 2702

Patent

active

047713232

ABSTRACT:
In a semiconductor memory device, a memory cell comprises a first MOS transistor (Q1) of a first channel type formed on a semiconductor substrate and having a gate electrode connected to a word line. A charge storage electrode is connected to the drain of the first transistor and forms a capacitor with the gate electrode. A semiconductor layer is formed over the charge storage electrode. A second MOS transistor (Q2) of a second channel type formed in the semiconductor layer. The charge storage electrode forms a gate electrode of the second transistor. The drain of the second transistor is connected to a power supply. The source of the second transistor is connected to a bit line, which is either the same as or separate from the first-mentioned bit line. For writing data, a first potential is applied to the word line to make conductive the first transistor for writing data, and the potential applied to the source of the first transistor is varied depending on whether the data to be written is "0" or "1". For maintaining the stored data, a second potential is applied to the word line to keep the first transistor nonconductive. For reading the stored data out, a third potential is applied to the word line to make the second transistor conductive or nonconductive depending on the data stored on the charge storage electrode.

REFERENCES:
patent: 4536785 (1985-08-01), Gibbons
patent: 4633438 (1986-12-01), Kume et al.
patent: 4669062 (1987-05-01), Nakano
Extended Abstracts of the 16th (1984) International Conference on Solid State Devices and Materials, Kobe 1984, pp. 265, "TITE RAM; A NEW SOI DRAM Gain Cell for M bit DRAM's" Shichijo, et al.

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