Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1993-01-14

1994-07-05

Popek, Joseph A.

Electric lamp and discharge devices: systems

Combined load device or load device temperature modifying...

Filament or electric heater in series with a discharge...

365203, 36518905, 36518907, G11C 1500

Patent

active

053273729

ABSTRACT:
A CAM cell array for storing a logical address is divided into first to third CAM sections. A first partition switch circuit intervenes between a zeroth piece of sense line connected to a sense circuit and a first piece of sense line for the first CAM section. The sense circuit is a circuit for selecting a RAM cell array in which a physical address to be read out is stored. A second partition switch circuit intervenes between the first piece of sense line and a second piece of sense line for the second CAM section. A third partition switch circuit intervenes between the second piece of sense line and a third piece of sense line for the third CAM section. By controlling switching operation of respective partition switch circuits according to page size, optimum length of the sense line is utilized, thus achieving a high-speed address translation.

REFERENCES:
patent: 4377855 (1983-03-01), Lavi
patent: 4453230 (1984-06-01), Mizoguchi et al.
patent: 4646271 (1987-02-01), Uchiyama et al.
patent: 4894799 (1990-01-01), Hanawa et al.
J. Miyaka et al., "A 40 MIPS (Peak) 64-bit Microprocessor with One-Clock Physical Cache Load/Store", ISSCC Digest of Technical Papers, pp. 42-43, Feb. 1990.

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