Semiconductor memory device

Static information storage and retrieval – Powering – Conservation of power

Patent

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Details

365226, 36523003, G11C 700

Patent

active

060317809

ABSTRACT:
A semiconductor memory device includes a plurality of memory arrays which are provided on a semiconductor chip, the memory arrays including a predetermined memory array. A plurality of bias-voltage supply circuits respectively supply operating voltages to the memory arrays, the bias-voltage supply circuits including a predetermined supply circuit which supplies an operating voltage to the predetermined memory array. A control circuit controls the bias-voltage supply circuits respectively when a command is externally transmitted to the control circuit. The control circuit outputs a disable signal to the predetermined supply circuit in response to a partial-sleep-mode set command externally transmitted thereto, the disable signal causing the predetermined supply circuit to stop supplying the operating voltage to the predetermined memory array. The control circuit outputs an enable signal to the predetermined supply circuit in response to a cancel command externally transmitted thereto, the enable signal causing the predetermined supply circuit to start the supply of the operating voltage to the predetermined memory array.

REFERENCES:
patent: 5384740 (1995-01-01), Etoh et al.
patent: 5490118 (1996-02-01), Nishioka et al.
patent: 5563839 (1996-10-01), Herdt et al.
patent: 5703475 (1997-12-01), Lee et al.

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