Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1988-01-29

1989-10-31

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

357 235, 357 41, G11C 1134, H01L 2978

Patent

active

048781991

ABSTRACT:
An electrically erasable-programmable read-only memory device has memory cells formed on a semiconductive substrate. Each memory cell has source and drain layers, and a floating gate electrode and a control gate electrode insulatively provided above the substrate. First and second well regions having a polarity opposite to that of the substrate are formed therein so that each well region contains one or a plurality of memory cells therein. When information stored in the memory cell or memory cells in the first well region is to be rewritten with new information in a partial data rewrite mode, a potential of the first well region is independently controlled so as to inhibit reading and writing of information in the memory cells in the first well region. A potential of the second well region is separately controlled so as to allow writing of the new information in the memory cells in the second well region. The new information is written in the memory cell or memory cells in the second well region. The written information can be subjected to a following normal data read operation. The memory cell or memory cells in the first well region become inactive thereafter.

REFERENCES:
patent: 4417325 (1983-11-01), Harari
patent: 4448400 (1984-05-01), Harari
patent: 4612629 (1986-09-01), Harari
patent: 4665418 (1987-05-01), Mizutani

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