Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2009-12-10

2011-12-13

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

C365S230060, C365S210100, C365S154000, C365S203000, C365S156000

Reexamination Certificate

active

08077493

ABSTRACT:
A semiconductor memory device includes a memory cell array disposing a plurality of memory cells at each intersection of word lines and bit lines, the memory cell including one pair of cross-connected inverters including a transistor, a first dummy transistor having a threshold voltage which has a certain relationship with a threshold voltage of the transistor of the memory cell, a dummy bit line connected to one end of the first dummy transistor, and the dummy bit line charged so as to have a predetermined voltage, a dummy transistor control circuit configured to control conduction of the first dummy transistor, and a word line driver configured to supply a word line voltage to the word line connected to the selected memory cell, and the word line driver configured to change a rise time of the word line voltage in accordance with a change in a voltage of the dummy bit line.

REFERENCES:
patent: 7054211 (2006-05-01), Tsujimura et al.
patent: 7193904 (2007-03-01), Joshi
patent: 7376032 (2008-05-01), Nguyen et al.
patent: 7570525 (2009-08-01), Nii et al.
Ohbayashi S. et al., A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits, IEEE 2006 Symposium on VLSI Circuits Digest of Technical Papers, in 2 pages.
Ishibashi, K. et al., A 1-V TFT-Load SRAM Using a Two-Step Word-Voltage Method, IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1519-1524.

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