Semiconductor memory device

Static information storage and retrieval – Format or disposition of elements

Reexamination Certificate

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C365S158000

Reexamination Certificate

active

08036010

ABSTRACT:
A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a plurality of memory cells arranged at intersections of the first lines and the second lines, each memory cell having one end connected to the first line and the other end connected to the second line; a first control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the first line to select and drive the first line; and a second control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the second line to select and drive the second line.

REFERENCES:
patent: 6972985 (2005-12-01), Rinerson et al.
patent: 2006/0023495 (2006-02-01), Rinerson et al.
patent: 2007-12160 (2007-01-01), None
patent: 2007-536680 (2007-12-01), None
patent: WO 02/078001 (2002-10-01), None
U.S. Appl. No. 12/708,822, filed Feb. 19, 2010, Tokiwa, et al.
Office Action issued Nov. 2, 2010 in JP Application No. 2008-068423 (With English Translation).
Mark Johnson, et al., “512-Mb PROM With a Three-Dimensional Array of Diode/Antifuse Memory Cells”, IEEE Journal of Solid-State Circuits, vol. 38, No. 11, Nov. 2003, pp. 1920-1928.

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