Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1992-12-02

1994-03-01

LaRoche, Eugene R.

Static information storage and retrieval

Format or disposition of elements

365 63, G11C 502

Patent

active

052914321

ABSTRACT:
A semiconductor memory device is provided having a read out gate for detecting and providing to a main I/O line pair the potential difference of a sub-data input/output line pair, and a write gate for transferring data of the main I/O line pair to the sub-data input/output line pair in an empty region surrounded by a sense amplifier region and a word line coupling region. By providing the read out gate and the write gate in the empty region which was not conventionally used, the access operation can be carried out at high speed without increasing the chip area of the semiconductor memory device.

REFERENCES:
patent: 4825418 (1989-04-01), Itoh
patent: 5097440 (1992-03-01), Konishi
"A 40ns 64Mb DRAM with Current-Sensing Data-Bus Amplifier", by Masao Taguchi et al., 1991 IEEE International Solid-State Circuits Conference, ISSCC91 Digest of Technical Papers, pp. 112-113.
"A 45ns 64Mb DRAM with a Merged Match-line Test Architecture", by Shigeru Mori et al., 1991 IEEE International Solid-State Circuits Conference, ISSCC91 Digest of Technical Papers, pp. 110-111.

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