Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-06-03

2010-10-26

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S233100, C365S189040, C365S191000, C365S109000, C365S145000

Reissue Patent

active

RE041879

ABSTRACT:
Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core6starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell1,in the memory core6,corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell1or a data write-in to the memory cell1is complete, a rewrite timer7is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell1.

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“Transistor Gijutsu Special” CQ Publishing Co., Ltd., Jan. 1, 1991, No. 25, pp. 23-27.

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