Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C257S309000

Reexamination Certificate

active

07859901

ABSTRACT:
A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

REFERENCES:
patent: 7355231 (2008-04-01), Coursey
patent: 2004/0165451 (2004-08-01), Wake
patent: 2006/0278951 (2006-12-01), Kim
patent: 2007/0183213 (2007-08-01), Kusakabe et al.
patent: 2005-191413 (2005-07-01), None

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