Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185230

Reexamination Certificate

active

07859913

ABSTRACT:
There is offered a semiconductor memory device that has reduced number of high withstand voltage transistors so as to suppress an increase in a die size. A second transistor of N channel type is connected between a word line and a decoder circuit. A control signal from a control circuit is applied to a gate of the second transistor. When an output of the decoder circuit is at a low level, the word line is in a non-selected state, and a high voltage from a switching circuit is not outputted to the word line. Instead, the word line is provided with the ground voltage (=non-erasing voltage) from the decoder circuit through the second transistor.

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patent: 5787037 (1998-07-01), Amanai
patent: 6201747 (2001-03-01), Venkatesh et al.
patent: 7016233 (2006-03-01), Kuo
patent: 11-274329 (1999-10-01), None
patent: 2000-173278 (2000-06-01), None
patent: 2005-159336 (2005-06-01), None

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