Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S230030, C365S185190, C365S189020

Reexamination Certificate

active

07835180

ABSTRACT:
A semiconductor memory device includes a plurality of banks, each configured to receive a bank operation control signal and perform predetermined operations in response to the received bank operation control signal, a plurality of bank control blocks, each configured to receive a bank sequential signal and generate the plurality of bank operation control signals in response to enable periods of the received bank sequential signal, and a bank sequential signal generating block configured to generate the plurality of bank sequential signals each having a multiplicity of enable periods that are sequential in response to a command signal.

REFERENCES:
patent: 2002/0018394 (2002-02-01), Takahashi
patent: 11-162161 (1999-06-01), None
patent: 10-2008-0052047 (2008-06-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Mar. 25, 2010.

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